This invention relates to an electrically programmable read only memory (hereinbelow, abbreviated to "EPROM").
Prior to this invention, an EPROM with its write-down efficiency enhanced has been proposed by the assignee of the present application as disclosed in the specification of Japanese Patent Application No. 55-87867 (J. Sugiura et al, "Semiconductor Device and Method for Fabricating the Same", U.S. patent application Ser. No. 277,393, filed June 25, 1981, German Patent Application No. P 31 24 283.9, British Patent Application No. 81.19691).
In the EPROM of Japanese Patent Application No. 55-87867, a non-volatile memory element thereof has a structure which includes a floating gate electrode and a control gate electrode overlying the floating gate electrode. A high impurity concentration region having the same conductivity type as that of the EPROM substrate is formed in that peripheral portion of the semiconductor surface of the non-volatile memory element which underlies a gate insulating film and which extends in a channel direction. In the non-volatile memory element of such structure, when a source-drain current flows during a write-down operation, the presence of the high impurity concentration region improves the generation efficiency of hot electrons, so that the write-down speed is enhanced.
The specification of the above-mentioned prior application, however, does not teach a construction which solves other problems in EPROMs. Further, a new problem has been found to exist in the structure formed with the high impurity concentration region as described above.
Specifically, the inventors' study has revealed that, to the end of raising the write-down efficiency of charges into a floating gate, a write-down voltage to be applied to a non-volatile memory element should desirably be a greater magnitude in a range in which a pn-junction does not substantially break down. However, when the high impurity concentration region is disposed as stated above, the pn-junction thus formed by the drain of the non-volatile memory element and the high impurity concentration can lead to avalanche breakdown even at a comparatively low reverse voltage. In a case where the pn-junction of the non-volatile memory element has undergone an avalanche breakdown due to a write-down voltage which is not satisfactorily controlled, holes created in the pn-junction due to the avalanche breakdown are injected into the interface between a silicon substrate and silicon dioxide underlying the floating gate of the non-volatile memory element. As a result, electrons which are injected by rewrite-down recombine with the holes in the floating gate, and the rewrite-down efficiency deteriorates. This has also been revealed by the inventors'' study. Accordingly, the write-down voltage level must be satisfactorily controlled.
In an integrated circuit, a plurality of non-volatile memory elements are disposed in a matrix form. The drains of a plurality of non-volatile memory elements arranged in the same column are coupled with a single bit line in common, while the control gates of a plurality of non-volatile memory elements arranged in the same row are coupled with a single word line in common. In accordance with such an arrangement, one non-volatile memory element is selected through a certain word line and a certain bit line.
In order to write down information into one non-volatile memory element, a write-down voltage is supplied to one bit line (selected bit line) with which the non-volatile memory element is coupled, and a word line signal at a selection level is supplied to one word line (selected word line). The high level of the write-down voltage is a comparatively high voltage, and it raises the potential of the floating gate to an unnegligible level through the parasitic capacitance between the drain and floating gate of the non-volatile memory element.
As a result, channel leakage currents flow to the non-selected non-volatile memory elements coupled with the selected bit line. The number of non-volatile elements to be coupled with one bit line increases in proportion to the increase of the memory capacity. Accordingly, the leakage currents increase with the increase of the memory capacity. In other words, in a case where the memory capacity has been increased, idle current increases, and this leads to high power consumption.
In addition to the above problem, when the leakage currents have increased excessively, the write-down current flowing to the selected non-volatile memory element decreases accordingly. Therefore, the current driving ability of the write-down circuit must be enhanced. This inevitably necessitates increasing the size of the elements which constitute the write-down circuit.
The leakage currents fluctuate by a comparatively large amount due to not only the manufacturing dispersions of the non-volatile memory elements but also because of the variation of an operating temperature. Accordingly, an appropriately designed write-down circuit is required. Unless such an appropriate write-down circuit is utilized, the product yield is reduced.
It has been found that the leakage currents can be reduced by connecting the sources of a plurality of non-volatile memory elements to the ground point of circuitry through a single common resistor (refer to T. Kihara et al, "Programmable Read Only Memory", U.S. patent application Ser. No. 193,411, filed Oct. 3, 1980, German Offenlegungsschrift No. 3,037,315). The inventors' study, however, has revealed a disadvantage of the prior approach in that since the magnitudes of the leakage currents depend upon the resistance of the common resistor, great dispersions are involved in the leakage currents in accordance with fluctuations in the manufacturing factors of the integrated circuit.